23 lines
379 B
Makefile
23 lines
379 B
Makefile
#target: dependency_1 dependency_2 dependency_3 ...
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# command
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#
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RM = /bin/rm -f
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OBJ = main.o file2char.o
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EXE = main
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CC = /usr/bin/gcc
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CFLAGS = -Wall
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#
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all: $(EXE)
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#
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$(EXE): $(OBJ)
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$(CC) $(CFLAGS) $(OBJ) -o $(EXE)
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#
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file2char.o: file2char.c file2char.h
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$(CC) -c file2char.c -o file2char.o
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#
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main.o: main.c file2char.h
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$(CC) -c main.c -o main.o
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#
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clean:
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$(RM) $(OBJ) $(EXE) *~
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